Crystalline Silicon

Increased Solar Conversion Efficiency:


Improvements in conversion efficiency lead to a proportional reduction in the amount of materials (glass, encapsulants, frame, racks) and labor required to produce a watt of power. Thus, improving efficiency can dramatically reduce cost. Current average industrial c-Si module efficiencies of ~15% are less than half the single-junction Shockley-Queisser limit (~33%), and less than a fifth of the thermodynamic solar energy conversion limit (~89%). Our research is aimed at closing the gap between current industrial efficiencies and these theoretical limits, using manufacturable processes.


Closing the gap with the Shockley-Queisser limit:
Two types of bulk defects strongly contribute to reducing the conversion efficiency of c-Si: iron impurities and dislocations. We are deepening our understanding of the nature and kinetics of these defects, and using simulation to develop manufacturing processes to detect, manipulate, passivate, and remove these defects. With collaborators at IES-UPM in Madrid, Spain, we developed the impurities to efficiency (I2E) simulation tool to predict the evolution of iron impurities during solar cell processing, allowing the optimization of both throughput and device efficiency. By annealing at high temperatures, we have demonstrated reductions in dislocation density that could bring mc-Si performance to parity with single-crystalline silicon for a negligible additional cost [1,2]. We are also investigating how mechanical stress, usually implicated in the creation of dislocations, can be carefully applied to increase the effectiveness of dislocation annealing [3].

[1] J. Hofstetter et al., Progress in Photovoltaics 19, 487–497 (2011)
[2] D.P. Fenning et al., Applied Physics Letters 98, 162103 (2011)


Enabling High-Quality Thin Si Substrates:

GFP The silicon material comprising the wafer accounts for roughly two fifths of the PV module cost [1]. Reducing wafer thickness from the industry-standard 180 µm down to 20–50 µm could greatly reduce cost and sensitivity to silicon price fluctuations. With industrial partners, we are developing thin wafering technologies that also eliminate the kerf, or sawdust, associated with the standard wire-sawing approach. Using the defect engineering approaches described above as well as new techniques to image stress distributions, reliably measure minority carrier lifetime, and define material defect tolerances in thin wafers, we will be able to potentially reduce silicon consumption by >10x without sacrificing performance or manufacturing yields.

[1] D.M. Powell, M.T. Winkler, H.J. Choi, C.B. Simmons, D. Berney Needleman, and T. Buonassisi, Energy & Environmental Science 5, 5874-5883 (2012).


Developing Cost-Effective Manufacturing Processes:


Current batch processing technologies are capital intensive, have low throughput, require significant labor and large factory floorprints, and are incompatible with thin wafers and high-efficiency device architectures. We are developing novel manufacturing technologies that blur the lines between traditional wafer, cell, and module manufacturing. Laser processing features prominently in our research portfolio, with emphases on the science of laser-materials interactions and associated simulation.

Our expertise with synchrotron-based micro X-Ray Fluorescence (μ-XRF) has allowed us to characterize the nanoscale interaction of silicon and impurities at different processing temperatures [3].  We recently validated experimentally that silicon-impurity systems can undergo melting upon cooling, also called ‘retrograde melting’ [4].  This result could enable the controlled creation of liquid metal-silicon droplets within or on the surface of a silicon matrix to engineer semiconductor-based systems via solid-liquid and vapor-liquid segregation.

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